Synchronization of Communication Systems Based on SDR
DOI:
https://doi.org/10.31649/mccs2022.05Keywords:
modulation, Field-Programmable Gate Array (FPGA), Hardware Description Language (HDL), synchronization, Bit Error Rate (BER), Error Vector Magnitude (EVM), Phase-Locked Loop (PLL)Abstract
The development of mobile telecommunications proceeds by increasing the productivity of communication systems, increasing the speed of information transmission, expanding the frequency band, and reducing delays. A software defined radio (SDR) is a programmable transceiver that supports various wireless technologies without the need for hardware upgrades. The best development environment for SDR devices is field-programmable gate arrays (FPGAs) because they provide parallel data processing. The signal in the communication channel is distorted under the influence of many factors: conversion of the signal sampling frequency in the transmitter and receiver, frequency and phase shift of the signal in the communication channel, signal delay, effect of white noise, etc. To reduce the impact of these effects, the receiver includes a synchronization circuit. The receiver contains the following units: automatic gain adjustment; frequency offset correction; recovery of symbol synchronization; restoration of the phase of the carrier frequency; signal demodulation. To ensure fulfillment of the Nyquist criteria and reduction of intersymbol distortions, the transmitter and receiver of the communication system contain a shaping filter with a characteristic of the square root of the raised cosine. Synchronization circles provide a certain range of changes in destabilizing factors. When this range is exceeded, the parameters and quality of the communication system deteriorate. The down-converter of the sampling frequency was studied, and its frequency characteristic was obtained. It is built on the basis of half-band filters according to the quadrature scheme. The frequency shift estimation and correction algorithm is developed according to the maximum likelihood criterion. The symbol synchronization recovery subsystem is based on a phase-locked-frequency circuit (PLL). The main characteristics of the PLL: the time to reach blocking; error detected; transient behavior and traceability; bandwidth. These options depend on the field of application and expected operating conditions. The bandwidth must be sufficient to compensate for deviations between the generator frequency and the reference input signal. The study of the time required by the PLL for synchronization with the reference signal was carried out. The coefficient of bit errors and the magnitude of the error vector for various frequency shifts in the communication channel are determined. The purpose of the article is to evaluate signal distortions in the HDL implementation of the communication system based on the Xilinx Zynq-7000 development environment.
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